Conventional LDMOS devices include a field isolation region underneath an edge of a polysilicon beat electrode. The drain region of the LDMOS device is offset from the gate electrode by the field isolation region. Positioning the field isolation region below the edge of the gate electrode improves device performance by distributing the potential voltage drop and reducing the electric field crowding in the substrate.
Recently, LDMOS devices have been introduced using shallow trench isolation (STI) technology to form the field isolation regions. In general, STI isolation improves the performance of submicron MOS devices, in part, by improving latch-up immunity and providing low junction capacitance. The advantage of employing STI technology in an LDMOS device relates to an ability to reduce the dimensions of the device. For example, high voltage devices are needed to drive the thin film transistors for LCD displays. Although, STI technology has been successfully introduced in submicron integrated circuits, when STI structures are fabricated in LDMOS devices, an undesirable increase in the on-resistance (Ron) is increased. Maintaining a low Ron is important to prevent power loss in an LDMOS device.
In addition to employing STI technology, further device improvements are centered on scaling down both the gate length of the transistor and the off-set distance of the drain region. Also, drain engineering techniques, such as doping level adjustments and the like, are employed. In addition to advanced drain engineering, significant reduction in Ron and improvement in transistor gain have been achieved by fabricating LDMOS devices on a strained silicon layer.
Although the use of STI, drain engineering, and strained silicon technology have operated to provide LDMOS devices having improved performance, additional improvements are necessary to overcome the Ron increase observed in LDMOS devices having STI regions.